1. Field of the Invention
The present disclosure relates to a semiconductor device and, more particularly, to a phase change memory device including resistant material and a method of fabricating the same.
2. Description of the Related Art
A semiconductor memory device may be classified as a volatile memory device or a non-volatile memory device depending on whether data stored in the memory device is erased when power to the device is turned off. Generally, a non-volatile memory device maintains data stored therein even when power is turned off. Accordingly, a non-volatile memory device is generally employed in applications that require the memory device to maintain stored data even during the event of a power loss. These applications may include, for example, a mobile memory device.
With the growing need for memory devices that are smaller in size but have large data storage capabilities, there is a high demand for highly integrated memory devices. As is well known, memory devices use memory cells to store data. Most memory cells are made of transistors that are turned on or off to store data. Alternatively, the memory cells may include phase change material.
A unit cell of the phase change memory device includes an access device and a data storage element serially connected to the access device. The data storage element includes a lower electrode electrically connected to the access device and a phase change material layer in contact with the lower electrode. Specifically, the phase change material layer is a material layer that electrically switches between an amorphous state and a crystalline state. The resistivity of the phase change material changes as the phase change material transitions from an amorphous state to a crystalline state and vice versa. The physical state of the phase change material may denote the type of data stored in the phase change memory cell. For example, when the phase change material layer is in an amorphous state (i.e., has high resistance); it generally denotes the storage of data ‘1’ in the cell. Alternatively, when the phase change material layer is in a crystalline state, (i.e., low resistance), it generally denotes the storage of data ‘O’ in the cell. The phase change material may change its state in response to a program current provided to the phase change material.
FIG. 1 is a cross-sectional view of a conventional phase change memory device. Referring to FIG. 1, a typical phase change memory device includes a lower interlayer insulating layer 12 disposed at a predetermined region of a semiconductor substrate 1, a lower electrode 14 passing through the lower interlayer insulating layer 12, an upper interlayer insulating layer 13 covering the surface of the lower interlayer insulating layer 12, a bit line 18 disposed on the upper interlayer insulating layer 13, a phase change pattern 16 disposed in the upper interlayer insulating layer 13 and in contact with the lower electrode 14, and an upper electrode 17 electrically connecting the phase change pattern 16 and the bit line 18. In addition, the lower electrode 14 is electrically connected to an access device such as a diode or a transistor.
When a program current flows through the lower electrode 14, Joule heat is generated at an interface (“an active contact surface”) between the phase change pattern 16 and the lower electrode 14. This Joule heat converts a part 20 of the phase change pattern 16 (“transition volume”) into an amorphous or crystalline state. A resistivity of the transition volume 20 in the amorphous state is higher than that of the transition volume 20 in the crystalline state. Therefore, whether information stored in a unit cell of the phase change memory device is logic “1” or logic “0” may be determined by sensing the current that flows through the transition volume 20 in a read mode.
In the structure described above, as the transition volume 20 increases, the program current has to increase proportionally. In this case, the access device should be designed to have a sufficient current driving capacity to supply the program current. However, to improve the current driving capacity, the area occupied by the access device should be increased. This in turn means that the overall size of the memory device needs to increase. This is contrary to the requirement of increasing the integration density of the memory device (i.e., the requirement to keep the memory device small.) There is therefore a need to keep the area of the transition volume 20 small so as to keep the overall size of the memory device small. In other words, a smaller transition volume 20 results in a higher integration density of the phase change memory device.
Methods of reducing the transition volume 20 are disclosed in U.S. Pat. No. 7,012,273 entitled “Phase Change Memory Device Employing Thermal-Electrical Contacts with Narrowing Electrical Current Paths” to Chen.
According to Chen, an upper electrode and a lower electrode which are spaced apart from each other are provided. A phase change layer is interposed between the upper electrode and the lower electrode. The lower electrode is disposed at a lower end part of a contact hole passing through an interlayer insulating layer. A sidewall of the contact hole above the lower electrode is covered with an insulating spacer. The phase change layer is disposed along the insulating spacer and a surface of the lower electrode. The upper electrode filling the contact hole is disposed above the phase change layer. In this case, a transition volume may be determined depending on the contact area between the lower electrode and the phase change layer. While the above described structure may contain the size of the transition volume, there is a need for a technique capable of further reducing the transition volume to be smaller is required.